Advanced  High-Speed Signal Propagation  

For Experienced Digital Designers, by
Dr. Howard Johnson

This is an advanced-level course for experienced digital designers who want to press their designs to the upper limits of speed and distance.

Focusing on lossy transmission environments like backplanes, cables and long on-chip interconnections, this two-day course teaches a unified theory of transmission impairments that apply to any transmission media.  This course is an advanced sequel toHigh-Speed Digital Design.

Main Topics

Skin effect	Lossy media
Dielectric loss	Single-ended and differential signaling
On-silicon transmission-line behavior	Frequency-domain modeling
Equalization	Signal distribution
Serial interconnections	Clock jitter

Course Syllabus

Fundamentals of time and frequency

• Characterize the types of simulation tools available to help you in your design, including the division between linear and non-linear analysis
• Review relations among time, frequency, and the physical extent of a circuit, including rules for dimensional scaling
• Introduce a theorem about maximal resonance

Lossy transmission line parameters

• Model a transmission structure using a cascade of simple linear elements
• Define the characteristic impedance and propagation function
• Trace the flow of returning signal current on an ideal, lossless transmission line
• Calculate DC resistance
• Evaluate AC resistance including skin effect, proximity effect and surface roughness
• Investigate dielectric losses
• Define two-port S-parameter representations of transmission structures, and show how they are used to compute system response
• Classroom demonstration: A transmission line is always a transmission line

Performance regions: on-silicon vs. off-chip

• Present the standard copper performance model
• Explore the hierarchy of transmission-line performance regions
• Study the lumped-element region, useful for understanding small interconnections and transmission-line imperfections
• On-chip connections use the RC region
• PCB interconnections use the skin-effect and dielectric-loss-limited regions
• Show the similarities and differences among the various regions
• Check conditions for existence of undesirable non-TEM modes
• Discuss the need for equalization, and show examples of equalizer circuits
• Investigate DC wander and circuits for DC restoration
• Example waveforms: 10 Gb/s serial link with PAM-4 coding and fully adaptive equalizer

Pcb trace design and connectors

• Dissect microstrip and stripline design tables
• Consider the effects of nickel plating and soldermask coating
• Estimate limits to the attainable length of a pcb trace operated at extreme speeds
• Compute the effects of impedance discontinuities caused by stubs and loads and learn to counteract these effects
• Characterize connectors
• Introduce the concept of tapering necessary for certain SMA connector applications
• Scrutinize the capacitance and inductance of a via, including the effect of pad-stripping, back-drilling, blind vias, and dangling via stubs
• Classroom demonstration: proximity effect for differential stripline traces
• Classroom movie: experiment showing inductance of vias, and effect of distance to the nearest inter-plane connection

Differential signaling

• Define differential and common-mode voltages, currents, impedance and differential S-parameters
• Present design tables for both edge-coupled and broadside-coupled differential traces
• Cite the specific advantages of differential signaling including improved tolerance to ground shifts, reduced radiation, and better tolerance of high-frequency losses
• Discuss management of differential skew

Clock distribution and jitter

• Review special requirements for clock signaling including low skew
• Consider means of attaining exceptionally low skew
• Emphasize the importance of terminating clock lines
• Provide advice on routing differential clocks
• Show why serpentine delays often deliver poor results
• Present strategies for driving multiple loads from one source
• Discuss the general issue of distributing high-quality signals to multiple loads
• Show how to construct and test a proper daisy-chain, "T", or "H" distribution
• Define clock jitter, clock jitter propagation, methods for measuring jitter, and the emerging issue of random versus deterministic jitter budgeting

Who should attend?

• Digital logic designers
• System architects
• Chip designers
• EMC specialists
• Applications engineers
• Anyone who works with digital logic at speeds in excess of 1GHz

 

This is a practical course. It is filled with practical examples and explanations. A basic understanding of the frequency domain representation of linear systems is assumed. Delegates without the benefit of formal training in analog circuit theory can use and apply the formulas and examples from this course. Delegates who have completed (at least) a first-year class in introductory linear circuit theory will comprehend the material at a deeper level.

Who Has Participated

Dr. Johnson has taught thousands of students at companies all over the world, including:

3Com	Honeywell	Nortel Networks
Agilent	IBM	Qualcomm
AMD	Innoveda	Rockwell-Collins
Boeing	Intel	Samsung
Cisco Systems	Lockheed Martin	Sandia National Labs
Compaq	Mentor Graphics	Sun Microsystems
Dell Computer	Motorola	Tektronix
Ericsson	NASA	Texas Instruments
Hewlett-Packard	Nokia	VLSI Logic

What People Are Saying

"Excellent real world practical information that will immediately impact my work." - Raytheon Engineer

"Cool class!. It explains all my mistakes." - Engineer, US Navy

"Management should attend this course to understand the importance of Signal Integrity for current and future products." - Hardware Engineer, ETAS GmbH

"Very practical! Real situations at exist at work. This analysis wil save us as things go faster." - Design Engineer, Hewlett Packard Laboratories

General schedule and registration