Dr. Howard Johnson last public seminar

Bypass Capacitor Sequencing

High-Speed Digital Design Online Newsletter: Vol. 9 Issue 07

My friend Bill just brought his family up for a visit that started with a little hiking and some river rafting. His son Ray, who had never handled a firearm before, was thrilled when I suggested we try target shooting with shotguns. We selected a skeet-shooting format. In this game, your pellets must meet a target flying through the air at about 30 mph. Ray blasted two of his first six targets. Pretty good for a first try. Ray says he has had "a lot" of videogame practice. At the end of the day, when no one was looking, Ray pocketed a spent shotgun shell as a souvenir of his visit.

I understand Ray's actions. Firearms are inherently dangerous. When an adult hands you a gun, it means that he respects you and believes you can carry the responsibility of handling the gun safely. That is a big moment for a young man.

Forty years ago, when my father first taught me to shoot, I pocketed a spent shell, too. It is a natural response in boys to hold on to some part of an activity that they enjoy.

Unfortunately for Ray, the spent shell was still in his jacket pocket when he and his family tried to pass through security at the airport, preparing for a flight to Germany...

Here is what I learned: things that worked just fine 40 years ago may no longer work in today's world. Somewhere along the line, the rules changed.

You will find a similar theme in this article about power supply layout.

 

Bypass Capacitor Sequencing

Carl Cooney writes (edited):

On a multilayer PCB, for any BGA or SMT package, how should I handle the VCC pin of my device?

  1. Tie the VCC pin directly to the VCC plane with a via, with the distance from the pin to the via as short as possible, and a decoupling capacitor located close by but separately tied with its own vias to the planes (Figure 1a), OR
  2. Route from a VCC plane via to the positive end of a decoupling capacitor and then from there sequence a short trace to the VCC pin of the device (Figure 1b).

I have the same question about a pin-grid-array (PGA) package.

Yours,
Carl Cooney

Carl, I like your first approach best (Figure 1a). The idea of sequencing your bypass connections from the VCC plane, to a bypass capacitor, and then to you IC power pin is very old. Those who advocate this approach usually justify the circuit (if there is any explanation at all) as an attempt to construct a filter network with the stated objective of "keeping power supply noise contained at the IC site, preventing it from getting out onto the larger pcb".

In the context of a high-speed digital pcb with solid power and ground planes, sequencing the bypass connection does not accomplish that goal. A power filter by itself does not prevent noise escaping into the pcb. Even if you power your IC from its own internal battery source, without involving the external power system at all, you still can't prevent noise escaping into the pcb because it couples into the pcb through the I/O traces of your IC.

A big IC has hundreds of I/O traces. Each trace enjoys a (nominally 50-ohm) connection directly from the trace to whichever is the nearest solid power or ground plane. Every time you wiggle a signal trace up or down, it pumps current straight into the power and/or ground planes of the pcb. You cannot avoid this behavior.

Power filters work to isolate sections of your system only when you cut off ALL OTHER means of intercommunication. Applying a power filter to an ordinary IC is like building an anti-immigration wall across southern California, but leaving huge swaths of Arizona, New Mexico and Texas wide open. The filter by itself does not stop anything.

Of course, power filters can, if properly designed, prevent noise flowing the other way. This is what you should do for a PLL, clock oscillator, clock recovery unit, or any other circuit particularly susceptible to power supply noise. You filter the power terminal of such sensitive components to keep noise from getting IN, not OUT. Such components usually have a limited number of connections coming in or out, and structures within the IC that block noise from entering through the I/O connections.

The only time a power filter helps prevent noise getting OUT of an IC is if the IC sucks down a huge amount of quick-changing, high-frequency current (like a big CPU), but has no other connections coming in or out. Few chips work that way.

My second objection to the sequencing structure in Figure 1b concerns its electrical behavior. Figure 2 shows an equivalent electrical network for the sequenced layout. In the electrical network, the trace connecting the bypass capacitor to the VCC pin acts as a small series inductance. If you use a 50-ohm trace on an FR-4 pcb, the inductance amounts to about 7 nH per inch. This trace also has some parasitic capacitance, but its value is negligible in this context.

Note that the inductor acts in SERIES with the IC power pin. Whatever current emanates from the IC passes straight through this inductance on its way to the capacitor. The inductor does not attenuate or otherwise modify the current—it just passes it right through. Therefore, the inductor in this circuit has absolutely no effect on the noise currents injected into the pcb power system UNLESS it somehow manages to change the current generated by the IC. And how might it do that?

The current demanded by an IC has to do with the number of I/O circuits switching, the configuration of loads connected to those outputs, and the switching speed at each output. Obviously, inductor L1 exerts no influence on either the number of loads or their configuration. All the inductor can possibly affect is the switching speed. It does this by inducing power supply droop at the VCC terminal of the IC. Every time the IC demands a surge of current, its VCC voltage droops temporarily by an amount related to value of L1.

A particularly severe VCC supply droop at the IC terminals will starve the internal gates for voltage to the point where they switch more slowly than normal, thus reducing the magnitude of power supply current spikes. Allowing any inductor to do this, in the name of reducing noise propagated to the VCC plane, is a monumentally bad idea. You should never permit so much power supply noise at the external VCC terminal of any digital circuit that you noticeably affect its output switching speed.

An IC designer, focused on minimizing the number of power and ground pins for his package, might permit an internal power supply droop at the I/O VCC rail inside the die of as much as perhaps 20 to 30% of VCC. You, as a pcb designer, do not have the luxury of doing that. You must meet the prescribed VCC tolerance of ±10, or in an increasing number of cases, an even tighter tolerance of ±5

I raise this subject because even a short trace between the bypass capacitor and your IC can cause surprising levels of power supply droop. Let's do an example. In a 1.5-V system, suppose your IC produces a 300 ps rise time when loaded with 50 ohms. If it drives ten such loads at once, the total change in current, going from the zero state to the high state, is 10*(1.5/50) = 300 mA. The change in current per unit time is (di/dt) = 300mA/300ps = 1E+09 A/s.

Passing this rate of change of current through an inductance of even 0.15 nH creates a voltage difference across the ends of that inductor of L*(di/dt) = 0.15 Volts, or ten percent of the power system voltage. That is the limit for most ICs. The maximum amount of inductance I can tolerate in L1 is therefore 0.15 nH.

Converting my budget of 0.15 nH into a trace length, assuming 7 nH per inch, the circuit requirements permit a trace length of at most 0.15/7 = 0.02 inches in length. Such a short trace is completely impractical.

So, if the layout in Figure 1b does not work well for modern high-speed digital devices, why do reasonable people still recommend it? I believe the main reason is that it worked beautifully on old two-layer boards. An old two-layer board lays out power and ground rails as a grid of traces. There are no solid planes. The whole power system is spaghetti-wired together. In such a system, even if you place a bypass capacitor right next to an IC, the auto-router may not hook them directly together. The power pin of the IC might route due east to a VCC trace on one side of the board, while the bypass capacitor routes due west to a VCC trace on the opposite side! This environment requires a sequencing rule that, first, ties the bypass capacitor straight to the IC, and then hooks them in common to the power system. In an older design, with rise times of perhaps 3 ns, and when driving loads much less power-hungry than 50-ohm traces, the short traces from bypass capacitor to IC did not create enough power-supply noise to worry about.

At today's speeds, a trace of any practical length placed in series with the power terminal of a high-speed IC (especially one with multiple VCC pins) radically increases power supply noise at the VCC terminal and should be avoided like the plague.

Connecting your IC power terminal straight to the planes replaces inductor L1 with the biggest, fattest, lowest-inductance connection you can make: the power and ground planes themselves. A connection made using the power plane is much wider than the trace (a fact you cannot discern in Figure 3), and remains much closer to the ground plane all along its length (a fact you can see in Figure 3). Both factors help reduce the inductance of the connection to the bypass capacitor.

Carl, I'll be in Raleigh, NC and a whole bunch of other cities soon doing my high-speed digital seminars. I hope we can talk in person about this.

Best regards,
Dr. Howard Johnson

For Further Study

Bypass Capacitor Layout www.sigcon.com/Pubs/straight/bypass.htm
Printed Circuit Design 1997
The primary symptoms of an inadequate, old-fashioned bypass capacitor array are increased power supply noise, increased crosstalk among signal traces, and increased electro-magnetic radiation.

Capacitor Placement www.sigcon.com/Pubs/news/2_1.htm
Newsletter 1998
The function of a bypass capacitor is this: to help returning signal current get from the board back into the driver.

Bypass Capacitor Layout www.sigcon.com/Pubs/news/2_3.htm
Newsletter 1998
Little traces between your bypass capacitors and the power planes have a big effect on performance.

Segmenting the VCC Plane www.sigcon.com/Pubs/news/2_18.htm
Newsletter 1998
I do not cut up the VCC plane unless I have one circuit that is substantially more sensitive to VCC noise than the other circuits on the board.

Parasitic Inductance of Bypass Capacitors www.sigcon.com/Pubs/edn/ParasiticInductance.htm
EDN 2000
You can estimate the parasitic series inductance of a bypass capacitor in a multi-layer board with solid power and ground planes.

Way Home www.sigcon.com/Pubs/edn/thewayhome.htm
EDN 2000
Current always makes a loop. If it goes out, it must find a way back home. The shapes of both the outgoig and returning paths affect the observed inductance.

Resonance in short transmission line www.sigcon.com/Pubs/news/6_06.htm
Newsletter 2003
Explores uses of the pi model for transmission line modeling.

Parasitic Inductance of Bypass Capacitor II www.sigcon.com/Pubs/news/6_09.htm
EDN 2003
The following values for the inductance of a surface-mounted bypass capacitor were collected using the step-response technique described in chapter 8 of High-Speed Digital Design.